(1) Field of the Invention
The invention relates to a pseudo SRAM, that is, a device having an interface that is compatible with a standard SRAM coupled with a memory array comprising dynamic memory cells, and, more particularly, to a pseudo SRAM integrated circuit a device having a partial data retention mode.
(2) Description of the Prior Art
Dynamic or DRAM memory devices use an array of memory cells with each cell typically comprising a single access transistor and a capacitor. By comparison, static or SRAM memory devices use an array of memory cells with each cell comprising multiple transistor cells, typically made up of 4 or 6 transistors. For this reason, DRAM memory devices are significantly smaller, and therefore less expensive, than SRAM devices for the same memory capacity. However, SRAM devices have lower current consumption since the DRAM cell capacitors must be frequently refreshed to hold their memory state. For example, a SRAM device having a memory capacity of 4 MB or 8 MB, will have a standby current, Istdby, of between about 20 xcexcA and 30 xcexcA. By comparison, a 16 MB or 32 MB memory based on dynamic memory cells will have an Istdby of between about 100 xcexcA and 150 xcexcA. This is too much current drain for many battery-based systems.
It remains desirable, however, from a cost reduction standpoint, to use DRAM memory devices rather than SRAM devices. For example, it is desirable to replace the low power SRAM in a portable electronics system or cell phone with a DRAM to reduce chip or system size and cost. To facilitate the substitution of DRAM for SRAM, with minimal impact on performance, the DRAM device must overcome two problems. First, the external access operations on the DRAM must be made compatible with those of a standard SRAM, and particularly the asynchronous SRAM, with very predictable results. Second, the current consumption problem must be minimized.
Referring now to FIG. 1, a prior art pseudo SRAM device 10 is illustrated in schematic form. In this prior art device, a SRAM compatible access control circuit 20 is used to access data from a static memory cell array 24 and a dynamic memory cell array 28. By incorporating both types of memory cell arrays 24 and 28, this approach gains part of the benefit of the lower integration cost of dynamic cells and part of the benefit of the lower standby current of static cells. In a typical arrangement, the dynamic array 28 is made substantially larger and is used to execute the bulk of active mode memory transactions. The static array 24 is made smaller and is used to hold data that must be maintained during a low-power mode condition.
In this configuration, the refresh controller 32 is used to refresh all of the cells in the dynamic memory array on a periodic basis to prevent memory state loss. This type of pseudo SRAM device may also have a power saving mode where the refresh controller 32 is turned OFF. In this state, all of the data in the dynamic array 28 is lost. Only data in the static array 24 is retained. A significant disadvantage of the prior art pseudo SRAM is the need for a static cell array 24 for the power saving mode. This static array 24 is not cost effective for the integrated circuit layout due to the larger cell size when compared to the dynamic cells. The inability to retain any data in the dynamic array also presents a serious application and programming limitation.
Several prior art inventions relate to refresh control for a DRAM device. U.S. Pat. 6,094,705 to Song describes a method and a system to reduce power consumption in a DRAM using selective refresh. The method uses valid bits associated with a row of the memory device to indicate if a refresh is required for that row. The method is not compatible with a standard SRAM, or pseudo SRAM, circuit. U.S. Pat. 5,724,295 to Beiley et al discloses a DRAM circuit to disable or to enable refresh for partitions of the DRAM memory array when redundant circuits are allocated. U.S. Pat. 6,311,280 to Vishin teaches a low power memory system for a portable digital radio. DRAM data rows may be selectively refreshed or not refreshed to save power.
A principal object of the present invention is to provide an effective and very manufacturable pseudo SRAM circuit.
A further object of the present invention is to provide a pseudo SRAM circuit comprising a SRAM compatible access controller and a dynamic memory array where the standby current consumption is reduced.
Another further object of the present invention is to provide a reduced standby current consumption pseudo SRAM device while providing partial data retention capability in the dynamic cell array.
Another further object of the present invention is to provide the increased flexibility of two power saving modes, one with partial data retention and one with no data retention.
Another further object of the present invention is to provide a circuit that is compatible with a dynamic memory only or a mixed, dynamic and static memory.
In accordance with the objects of this invention, a pseudo SRAM integrated circuit device is achieved. The device comprises, first, a memory array comprising a plurality of dynamic storage cells. In addition, an access controller is included. The access controller provides read and write access to the memory array from an external device. The access controller performance is compatible with a standard SRAM memory device. The access controller enables a partial data retention mode comprising selective refreshing of at least one part of the memory array and non-refreshing of at least one other part of the memory array.